The following relates to the lighting arts. It especially relates to high intensity light emitting diode chip packages, and to methods for producing such packages, and will be described with particular reference thereto. However, the following will also find application in conjunction with other solid state light emitting chip packages such as vertical cavity surface emitting laser packages, in conjunction with solid state electronics packaging, and the like.
One issue in light emitting chip packaging is scalability. A light emitting chip, such as a light emitting diode chip or a laser diode chip, is generally a relatively small light source. Moreover, while light output efficiencies continue to improve due to improved chip designs, a single light emitting chip may be inadequate for some high intensity illumination applications. Accordingly, a plurality of light emitting chips are sometimes arranged in an array, strip, or other configuration to provide higher cumulative illumination intensities and/or to provide spatially extended light sources. Depending on the light output of each chip, and the illumination intensity and characteristics required by the application, different numbers and arrangements of light emitting chips are used.
Another issue in light emitting chip packaging is the mounting arrangement. If the package includes solderable leads, these leads should be well-separated from one another to promote soldering without shorting across the leads. In one common design, a lead flame has a first lead including cup receiving the light emitting chip, and a second lead. The light emitting chip is connected with the leads by wire bonding, and an encapsulant is disposed over the chip and ends of both leads to secure them together. The distal ends of the leads extend outside of the encapsulant for soldering connection.
In some applications, a surface mount package is preferred, in which solderable bonding pads are disposed on the backside of the package opposite the light-emitting side. In one approach, a sub-mount supports the light emitting chip on one side, and has the bonding pads disposed on the backside of the sub-mount. To connect the light emitting chip on the frontside with the backside bonding pads, vias are formed through the sub-mount.
Yet another issue in light emitting chip packaging is thermal heat sinking. The sub-mount, if used, is generally a thermally conductive material to promote heat extraction from the light emitting chip. Some of the highest thermal conductivity materials, such as metals, are also electrically conductive; however, the sub-mount generally should be electrically insulative. Hence, the sub-mount is typically made of a thermally conductive but electrically insulating material such as a ceramic, silicon carbide, sapphire, or the like.
Many of these issues also pertain to non-optical chip packages, such as integrated circuit (IC) chip packages. In particular, such packages sometimes generate a substantial amount of heat, and it is sometimes advantageous for such packages to be surface mountable. Moreover, if the package includes a large number of IC chips, it is advantageous for the chips to be arranged in a rectangular array or other compact configuration so as to readily fit into a device housing or other confined space.
The following contemplates improved apparatuses and methods that overcome the above-mentioned limitations and others.